Handheld battery powered electronic devices such as tablets and smartphones have been in wide use in recent years, with usage rates that are ever increasing, and with additional functionality being added on a regular basis.
A common type of voltage regulator used in such electronic devices is known as a low dropout (LDO) regulator, which can operate with a small input to output voltage difference, and which provides a high degree of efficiency and heat dissipation. A typical LDO regulator includes an error amplifier that controls a field effect transistor (FET) or bipolar junction transistor (BJT) to cause that transistor to sink or source current from or to an output node. One input of the error amplifier receives a feedback signal, while the other receives a reference voltage. The error amplifier controls the power FET or BJT so as to maintain a constant output voltage.
The power FET or BJT is typically tolerant of 5V, meaning that the FET or BJT therefore has a large area and a low transconductance, however to source or sink a high current, a large transconductance would be required, leading to a very large sized transistor. This in turn leads to high leakage current when the LDO is powered down. In addition, the bandwidth of the LDO is limited by a high input gate or base capacitance to the power FET or BJT. Another drawback of this design is that the power FET or BJT has a large gate to drain or base to emitter capacitance and total gate or drain capacitance due to its size, which results in degradation in high frequency power source noise rejection.
In an attempt to address these drawbacks, additional designs have been devised. For example, a LDO 100 is shown in FIG. 1. In this LDO, amplifier 102 has its inverting terminal coupled to a reference voltage Vref, its non-inverting terminal coupled to receive a feedback voltage Vfb, and its output coupled to the gate of p-channel transistor T1. P-channel transistor T1 has its source coupled to a supply voltage Vdd and its drain coupled to node N1. P-channel transistor T2 has its source coupled to node N1, its drain coupled to provide the output of the LDO Vout at node N3, and its gate coupled to the output of amplifier 104. Amplifier 104 has its inverting terminal coupled to node N1 and its non-inverting terminal coupled to receive comparison voltage Vc. A resistive divider formed from series coupled resistances R1 and R2 is coupled between node N3 and ground. A center tap N2 of the resistive divider formed by R1 and R2 is coupled to the non-inverting terminal of amplifier 102 to provide the feedback voltage Vfb thereto.
The transistors T1 and T2 are low voltage devices, and are to be protected from electrical overstresses. When the LDO 100 is operating in a normal power on mode, T2 is biased by amplifier 104 such that it acts as a switch. When the LDO 100 is powered down, node N1 is biased such that neither T1 nor T2 experiences overstresses. However, during the transition between the powered on mode and the powered down mode, or between the powered down mode and the powered on mode, node N1 can intermittently go to supply or ground at a different time constant than node N3, which can also go to ground. Transistor T1 can be stressed because it has no protections against such overstresses, and transistor T2 can be stressed because it is within the feedback loop.
Further development of LDO regulators is necessary to address the aforementioned drawbacks.